The present invention relates to a semiconductor device in which multiple elements are integrated on a semiconductor substrate, and an electronic device having the semiconductor device mounted thereon, and more particularly to a method of testing an open failure of a supply terminal or a ground terminal disposed on the semiconductor device.
As a technique for testing the open failure of the supply terminal or the ground terminal, for example, a method disclosed in Japanese Patent Unexamined Application Publication No. Hei 11(1999)-237441 has been known. This publication discloses a technique of testing whether or not all of multiple supply terminals or ground terminals disposed on a semiconductor package are normally coupled to joint portions on a printed circuit board. More specifically, there is provided a detector for electrically detecting a coupling state of multiple the terminals on the semiconductor package to multiple the joint portions on the printed circuit board, which face the respective terminals.
The same technique is disclosed in Japanese Patent Unexamined Application Publication No. 2005-322768. An (large scale integration) chip disclosed in this publication includes multiple pads, an internal wiring coupled to the pads, a monitor circuit coupled to the pads, and a detector circuit coupled to the monitor circuit. The monitor circuit outputs multiple measurement signals indicative of values corresponding to the respective potentials of those pads to the detector circuit. The detector circuit detects differences of the potentials among the plural pads on the basis of input measurement signals.